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Complete Serial port

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SukkoPera
2019-04-17 22:23:04 +02:00
parent ea55c9a3fd
commit 9bb25736e5
5 changed files with 1242 additions and 727 deletions
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119
Raemix500-cache.lib
View File

@@ -716,6 +716,26 @@ X R5.1 9 600 -200 150 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Diode_1N4148
#
DEF Diode_1N4148 D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Diode_1N4148" 0 -100 50 H V C CNN
F2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" 0 -175 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 1N4448 1N4149 1N4151 1N914 BA243 BA244 BA282 BA283 BAV17 BAV18 BAV19 BAV20 BAV21 BAW75 BAW76 BAY93
$FPLIST
D*DO?35*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 50 -50 -50 N
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# FAT_AGNUS_8375_FAT_AGNUS_8375
#
DEF FAT_AGNUS_8375_FAT_AGNUS_8375 U 0 40 Y Y 2 F N
@@ -940,34 +960,43 @@ ENDDEF
#
# MC1488_MC1488
#
DEF MC1488_MC1488 U 0 40 Y Y 5 F N
DEF MC1488_MC1488 U 0 40 Y N 5 F N
F0 "U" 0 250 50 H V C CNN
F1 "MC1488_MC1488" 0 150 50 H V C CNN
F2 "MODULE" 0 -250 50 H I C CNN
F3 "DOCUMENTATION" 0 -350 50 H I C CNN
DRAW
A 0 0 112 634 -634 1 1 6 N 50 100 50 -100
S -450 -250 450 250 2 0 0 N
S -450 -250 450 250 3 0 0 N
S -450 -250 450 250 4 0 0 N
S -500 -200 500 200 5 0 0 N
A 0 0 112 634 -634 2 1 6 N 50 100 50 -100
A 0 0 112 634 -634 3 1 6 N 50 100 50 -100
A 0 0 112 634 -634 4 1 6 N 50 100 50 -100
S -100 -100 100 100 5 0 0 N
P 2 1 1 6 -150 100 50 100 N
P 2 1 1 6 100 -50 150 0 N
P 3 1 1 6 -150 100 -150 -100 50 -100 N
P 2 2 1 6 -150 100 50 100 N
P 2 2 1 6 100 -50 150 0 N
P 3 2 1 6 -150 100 -150 -100 50 -100 N
P 2 3 1 6 -150 100 50 100 N
P 2 3 1 6 100 -50 150 0 N
P 3 3 1 6 -150 100 -150 -100 50 -100 N
P 2 4 1 6 -150 100 50 100 N
P 2 4 1 6 100 -50 150 0 N
P 3 4 1 6 -150 100 -150 -100 50 -100 N
X ~ 2 -300 0 146 R 50 50 1 1 I
X ~ 3 250 0 138 L 50 50 1 1 O
X IN1_B 4 -750 50 300 R 50 50 2 1 I
X IN2_B 5 -750 -50 300 R 50 50 2 1 I
X OUT_B 6 750 -50 300 L 50 50 2 1 O
X IN1_C 10 -750 -50 300 R 50 50 3 1 I
X OUT_C 8 750 -50 300 L 50 50 3 1 O
X IN2_C 9 -750 50 300 R 50 50 3 1 I
X OUT_D 11 750 -50 300 L 50 50 4 1 O
X IN2_D 12 -750 50 300 R 50 50 4 1 I
X IN1_D 13 -750 -50 300 R 50 50 4 1 I
X VEE 1 0 -500 300 U 50 50 5 1 W
X VCC 14 0 500 300 D 50 50 5 1 W
X GND 7 -800 0 300 R 50 50 5 1 W
X IN1_B 4 -300 -50 146 R 50 50 2 1 I
X IN2_B 5 -300 50 146 R 50 50 2 1 I
X OUT_B 6 250 0 138 L 50 50 2 1 O
X IN1_C 10 -300 50 146 R 50 50 3 1 I
X OUT_C 8 250 0 138 L 50 50 3 1 O
X IN2_C 9 -300 -50 146 R 50 50 3 1 I
X OUT_D 11 250 0 138 L 50 50 4 1 O
X IN2_D 12 -300 -50 146 R 50 50 4 1 I
X IN1_D 13 -300 50 146 R 50 50 4 1 I
X VEE 1 50 250 146 D 50 50 5 1 W
X VCC 14 -50 250 146 D 50 50 5 1 W
X GND 7 0 -250 146 U 50 50 5 1 W
ENDDRAW
ENDDEF
#
@@ -1084,6 +1113,28 @@ X GND 8 0 -1300 300 U 50 50 2 1 W
ENDDRAW
ENDDEF
#
# Transistor_BJT_2N3904
#
DEF Transistor_BJT_2N3904 Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT_2N3904" 200 0 50 H V L CNN
F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
$FPLIST
TO?92*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X E 1 100 -200 100 U 50 50 1 1 P
X B 2 -200 0 225 R 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# VIA_8520_VIA_8520
#
DEF VIA_8520_VIA_8520 U 0 40 Y Y 2 F N
@@ -1515,6 +1566,40 @@ X 3 3 300 100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# mc1489_MC1489
#
DEF mc1489_MC1489 U 0 40 Y N 5 F N
F0 "U" -50 0 50 H V C CNN
F1 "mc1489_MC1489" -50 -150 50 H V C CNN
F2 "MODULE" 0 -250 50 H I C CNN
F3 "DOCUMENTATION" 0 -350 50 H I C CNN
DRAW
S -50 -100 50 100 5 0 0 N
P 2 1 1 6 -150 100 50 0 N
P 3 1 1 6 -150 100 -150 -100 50 0 N
P 2 2 1 6 -150 100 50 0 N
P 3 2 1 6 -150 100 -150 -100 50 0 N
P 2 3 1 6 -150 100 50 0 N
P 3 3 1 6 -150 100 -150 -100 50 0 N
P 2 4 1 6 -150 100 50 0 N
P 3 4 1 6 -150 100 -150 -100 50 0 N
X IN_A 1 -300 0 146 R 50 50 1 1 I
X CTL_A 2 0 100 75 D 50 50 1 1 I
X OUT_A 3 200 0 146 L 50 50 1 1 O
X IN_B 4 -300 0 146 R 50 50 2 1 I
X CTL_A 5 0 100 75 D 50 50 2 1 I
X OUT_B 6 200 0 146 L 50 50 2 1 O
X IN_C 10 -300 0 146 R 50 50 3 1 I
X OUT_C 8 200 0 146 L 50 50 3 1 O
X CTL_A 9 0 100 75 D 50 50 3 1 I
X OUT_D 11 200 0 146 L 50 50 4 1 O
X CTL_A 12 0 100 75 D 50 50 4 1 I
X IN_D 13 -300 0 146 R 50 50 4 1 I
X VCC 14 0 250 146 D 50 50 5 1 W
X GND 7 0 -250 146 U 50 50 5 1 W
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P

4
audio.sch
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@@ -2378,12 +2378,12 @@ Wire Notes Line
15380 1555 14840 1555
Wire Notes Line
14840 1555 14840 1135
Text Notes 9045 10220 2 50 ~ 0
This whole circuit has some\ndifferent values on A600.
Wire Bus Line
1955 4305 1955 4505
Wire Bus Line
1955 6355 1955 7055
Wire Bus Line
1955 4705 1955 6205
Text Notes 9045 10220 2 50 ~ 0
This whole circuit has some\ndifferent values on A600.
$EndSCHEMATC

1802
cias.sch
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File diff suppressed because it is too large Load Diff

43
libs/MC1488.lib
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@@ -3,34 +3,43 @@ EESchema-LIBRARY Version 2.4
#
# MC1488
#
DEF MC1488 U 0 40 Y Y 5 F N
DEF MC1488 U 0 40 Y N 5 F N
F0 "U" 0 250 50 H V C CNN
F1 "MC1488" 0 150 50 H V C CNN
F2 "MODULE" 0 -250 50 H I C CNN
F3 "DOCUMENTATION" 0 -350 50 H I C CNN
DRAW
A 0 0 112 634 -634 1 1 6 N 50 100 50 -100
S -450 -250 450 250 2 0 0 N
S -450 -250 450 250 3 0 0 N
S -450 -250 450 250 4 0 0 N
S -500 -200 500 200 5 0 0 N
A 0 0 112 634 -634 2 1 6 N 50 100 50 -100
A 0 0 112 634 -634 3 1 6 N 50 100 50 -100
A 0 0 112 634 -634 4 1 6 N 50 100 50 -100
S -100 -100 100 100 5 0 0 N
P 2 1 1 6 -150 100 50 100 N
P 2 1 1 6 100 -50 150 0 N
P 3 1 1 6 -150 100 -150 -100 50 -100 N
P 2 2 1 6 -150 100 50 100 N
P 2 2 1 6 100 -50 150 0 N
P 3 2 1 6 -150 100 -150 -100 50 -100 N
P 2 3 1 6 -150 100 50 100 N
P 2 3 1 6 100 -50 150 0 N
P 3 3 1 6 -150 100 -150 -100 50 -100 N
P 2 4 1 6 -150 100 50 100 N
P 2 4 1 6 100 -50 150 0 N
P 3 4 1 6 -150 100 -150 -100 50 -100 N
X ~ 2 -300 0 146 R 50 50 1 1 I
X ~ 3 250 0 138 L 50 50 1 1 O
X IN1_B 4 -750 50 300 R 50 50 2 1 I
X IN2_B 5 -750 -50 300 R 50 50 2 1 I
X OUT_B 6 750 -50 300 L 50 50 2 1 O
X IN1_C 10 -750 -50 300 R 50 50 3 1 I
X OUT_C 8 750 -50 300 L 50 50 3 1 O
X IN2_C 9 -750 50 300 R 50 50 3 1 I
X OUT_D 11 750 -50 300 L 50 50 4 1 O
X IN2_D 12 -750 50 300 R 50 50 4 1 I
X IN1_D 13 -750 -50 300 R 50 50 4 1 I
X VEE 1 0 -500 300 U 50 50 5 1 W
X VCC 14 0 500 300 D 50 50 5 1 W
X GND 7 -800 0 300 R 50 50 5 1 W
X IN1_B 4 -300 -50 146 R 50 50 2 1 I
X IN2_B 5 -300 50 146 R 50 50 2 1 I
X OUT_B 6 250 0 138 L 50 50 2 1 O
X IN1_C 10 -300 50 146 R 50 50 3 1 I
X OUT_C 8 250 0 138 L 50 50 3 1 O
X IN2_C 9 -300 -50 146 R 50 50 3 1 I
X OUT_D 11 250 0 138 L 50 50 4 1 O
X IN2_D 12 -300 -50 146 R 50 50 4 1 I
X IN1_D 13 -300 50 146 R 50 50 4 1 I
X VEE 1 50 250 146 D 50 50 5 1 W
X VCC 14 -50 250 146 D 50 50 5 1 W
X GND 7 0 -250 146 U 50 50 5 1 W
ENDDRAW
ENDDEF
#

1
sym-lib-table
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@@ -19,4 +19,5 @@
(lib (name db25_female_mountingholes)(type Legacy)(uri ${KIPRJMOD}/libs/db25_female_mountingholes.lib)(options "")(descr ""))
(lib (name emi_filter_lcl_small)(type Legacy)(uri ${KIPRJMOD}/libs/emi_filter_lcl_small.lib)(options "")(descr ""))
(lib (name db25_male_mountingholes)(type Legacy)(uri ${KIPRJMOD}/libs/db25_male_mountingholes.lib)(options "")(descr ""))
(lib (name mc1489)(type Legacy)(uri ${KIPRJMOD}/libs/mc1489.lib)(options "")(descr ""))
)