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gatemate: fix static and handle dynamic FIFO almost full/empty offsets (#1555)

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* gatemate/pack_bram: fix CC_FIFO_40K almost full/empty parameters

* gatemate/pack_bram: fifo read/write pointers are 16 bit wide

* gatemate/pack_bram: handle dynamic almost full/empty offsets
This commit is contained in:
Patrick Urban 2025-09-12 15:02:28 +02:00 committed by GitHub
parent b8d2372019
commit 00cf81e463
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GPG Key ID: B5690EEEBB952194
1 changed files with 15 additions and 7 deletions
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22
himbaechel/uarch/gatemate/pack_bram.cc
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@ -361,7 +361,7 @@ void GateMatePacker::pack_ram()
log_error("The FIFO configuration of A_WIDTH and B_WIDTH must be equal.\n"); log_error("The FIFO configuration of A_WIDTH and B_WIDTH must be equal.\n");
if (a_rd_width != 80 && ram_mode == 1) if (a_rd_width != 80 && ram_mode == 1)
log_error("FIFO SDP is ony supported in 80 bit mode.\n"); log_error("FIFO SDP is only supported in 80 bit mode.\n");
ci.params[id_RAM_cfg_input_config_b0] = Property(width_to_config(b_wr_width), 3); ci.params[id_RAM_cfg_input_config_b0] = Property(width_to_config(b_wr_width), 3);
ci.params[id_RAM_cfg_output_config_a0] = Property(width_to_config(a_rd_width), 3); ci.params[id_RAM_cfg_output_config_a0] = Property(width_to_config(a_rd_width), 3);
@ -377,19 +377,27 @@ void GateMatePacker::pack_ram()
else else
ci.params[id_RAM_cfg_fifo_async_enable] = Property(0b1, 1); ci.params[id_RAM_cfg_fifo_async_enable] = Property(0b1, 1);
// TODO: Handle dynamic almost empty/full
int dyn_stat_select = int_or_default(ci.params, id_DYN_STAT_SELECT, 0); int dyn_stat_select = int_or_default(ci.params, id_DYN_STAT_SELECT, 0);
if (dyn_stat_select != 0 && dyn_stat_select != 1) if (dyn_stat_select != 0 && dyn_stat_select != 1)
log_error("DYN_STAT_SELECT must be 0 or 1.\n"); log_error("DYN_STAT_SELECT must be 0 or 1.\n");
if (dyn_stat_select != 0 && ram_mode == 1) if (dyn_stat_select != 0 && ram_mode == 1)
log_error("Dynamic FIFO offset configuration is not supported in SDP mode.\n"); log_error("Dynamic FIFO offset configuration is not supported in SDP mode.\n");
if (dyn_stat_select != 0)
log_error("Dynamic FIFO offset configuration is currently not supported.\n");
ci.params[id_RAM_cfg_dyn_stat_select] = Property(dyn_stat_select << 1, 2); ci.params[id_RAM_cfg_dyn_stat_select] = Property(dyn_stat_select << 1, 2);
ci.params[id_RAM_cfg_almost_empty_offset] = ci.params[id_RAM_cfg_almost_empty_offset] =
Property(int_or_default(ci.params, id_F_ALMOST_EMPTY_OFFSET, 0), 15); Property(int_or_default(ci.params, id_ALMOST_EMPTY_OFFSET, 0), 15);
ci.params[id_RAM_cfg_almost_full_offset] = ci.params[id_RAM_cfg_almost_full_offset] =
Property(int_or_default(ci.params, id_F_ALMOST_FULL_OFFSET, 0), 15); Property(int_or_default(ci.params, id_ALMOST_FULL_OFFSET, 0), 15);
if (dyn_stat_select != 0 && ram_mode == 0) {
for (int i = 0; i < 15; ++i) {
// WEA[14:0] = F_ALMOST_EMPTY_OFFSET
ci.disconnectPort(ctx->idf("WEA[%d]", i));
ci.renamePort(ctx->idf("F_ALMOST_EMPTY_OFFSET[%d]", i), ctx->idf("WEA[%d]", i));
// WEA[34:20] = F_ALMOST_FULL_OFFSET
ci.disconnectPort(ctx->idf("WEA[%d]", 20 + i));
ci.renamePort(ctx->idf("F_ALMOST_FULL_OFFSET[%d]", i), ctx->idf("WEA[%d]", 20 + i));
}
}
} }
for (int i = 0; i < 40; i++) { for (int i = 0; i < 40; i++) {
@ -446,7 +454,7 @@ void GateMatePacker::pack_ram()
ci.renamePort(id_F_RST_N, ctx->id("F_RSTN")); ci.renamePort(id_F_RST_N, ctx->id("F_RSTN"));
move_ram_o(&ci, ctx->id("F_RSTN")); move_ram_o(&ci, ctx->id("F_RSTN"));
for (int i = 0; i < 15; i++) { for (int i = 0; i < 16; i++) {
ci.renamePort(ctx->idf("F_RD_PTR[%d]", i), ctx->idf("FRD_ADDR[%d]", i)); ci.renamePort(ctx->idf("F_RD_PTR[%d]", i), ctx->idf("FRD_ADDR[%d]", i));
move_ram_i(&ci, ctx->idf("FRD_ADDR[%d]", i)); move_ram_i(&ci, ctx->idf("FRD_ADDR[%d]", i));