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timing: Improve clock constraint log output

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
2018-11-26 18:56:10 +00:00
parent 86108bfd39
commit 0adc0d7529
1 changed files with 6 additions and 2 deletions
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8
common/nextpnr.cc
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@@ -409,12 +409,16 @@ void Context::check() const
void BaseCtx::addClock(IdString net, float freq)
{
log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
std::unique_ptr<ClockConstraint> cc(new ClockConstraint());
cc->period = getCtx()->getDelayFromNS(1000 / freq);
cc->high = getCtx()->getDelayFromNS(500 / freq);
cc->low = getCtx()->getDelayFromNS(500 / freq);
nets.at(net)->clkconstr = std::move(cc);
if (!nets.count(net)) {
log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
} else {
nets.at(net)->clkconstr = std::move(cc);
log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
}
}
NEXTPNR_NAMESPACE_END