github.com/YosysHQ.nextpnr
1
0
Fork 0
mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-02-15 20:36:31 +00:00
Code Issues Releases Wiki Activity

Small fixes

Browse Source
This commit is contained in:
Miodrag Milanovic
2025-06-23 08:07:16 +02:00
parent 96b029d560
commit 23ca3cd2b3
2 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@@ -159,10 +159,10 @@ def set_timings(ch):
lut.add_comb_arc("IN4", "OUT", TimingValue(443, 453)) # to OUT2
lut = ch.timing.add_cell_variant(speed, "CPE_L2T5")
lut.add_comb_arc("IN1", "OUT2", TimingValue(479, 484)) # to OUT2
lut.add_comb_arc("IN2", "OUT2", TimingValue(471, 488)) # to OUT2
lut.add_comb_arc("IN3", "OUT2", TimingValue(446, 449)) # to OUT2
lut.add_comb_arc("IN4", "OUT2", TimingValue(443, 453)) # to OUT2
lut.add_comb_arc("IN1", "OUT1", TimingValue(479, 484)) # to OUT2
lut.add_comb_arc("IN2", "OUT1", TimingValue(471, 488)) # to OUT2
lut.add_comb_arc("IN3", "OUT1", TimingValue(446, 449)) # to OUT2
lut.add_comb_arc("IN4", "OUT1", TimingValue(443, 453)) # to OUT2
lut.add_comb_arc("IN5", "OUT1", TimingValue(416, 418)) # IN5 to OUT1
lut.add_comb_arc("IN6", "OUT1", TimingValue(413, 422)) # IN6 to OUT1
lut.add_comb_arc("IN7", "OUT1", TimingValue(372, 374)) # IN7 to OUT1

2
himbaechel/uarch/gatemate/pack.cc
View File

@@ -141,7 +141,7 @@ std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_io(CellInfo *cell, IdStr
if (!i_net && !o_net)
return std::make_pair(nullptr, nullptr);
CellInfo *cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), oPort.c_str(ctx)));
CellInfo *cpe_ramio = create_cell_ptr(id_CPE_RAMIO, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), oPort.c_str(ctx)));
if (place) {
cell->constr_children.push_back(cpe_ramio);
cpe_ramio->cluster = cell->cluster;