mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-04-28 21:07:15 +00:00
Cleanup
This commit is contained in:
@@ -257,7 +257,7 @@ struct BitstreamBackend
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dict<IdString, Property> params = cell.second->params;
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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if (l.z == 0) {
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if (l.z == CPE_LT_U_Z) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
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@@ -270,7 +270,7 @@ struct BitstreamBackend
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
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}
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}
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if (l.z == 7) {
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if (l.z == CPE_LT_FULL_Z) {
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if (cell.second->type.in(id_CPE_MX4)) {
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update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params);
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update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params);
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@@ -305,7 +305,7 @@ struct BitstreamBackend
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for (auto &p : params) {
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IdString name = p.first;
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switch (l.z) {
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case 1: // CPE_LT_L
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case CPE_LT_L_Z:
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switch (p.first.index) {
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case id_INIT_L00.index:
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name = id_INIT_L02;
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@@ -318,7 +318,7 @@ struct BitstreamBackend
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break;
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}
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break;
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case 4: // CPE_RAMIO_U
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case CPE_RAMIO_U_Z:
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switch (p.first.index) {
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case id_C_RAM_I.index:
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name = id_C_RAM_I2;
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@@ -328,7 +328,7 @@ struct BitstreamBackend
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break;
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}
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break;
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case 5: // CPE_RAMIO_L
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case CPE_RAMIO_L_Z:
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switch (p.first.index) {
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case id_C_RAM_I.index:
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name = id_C_RAM_I1;
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@@ -85,6 +85,18 @@ enum CPEFunction
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C_ADDCIN = 7,
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};
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enum CPE_Z
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{
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CPE_LT_U_Z = 0,
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CPE_LT_L_Z = 1,
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CPE_FF_U_Z = 2,
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CPE_FF_L_Z = 3,
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CPE_RAMIO_U_Z = 4,
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CPE_RAMIO_L_Z = 5,
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CPE_LINES_Z = 6,
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CPE_LT_FULL_Z = 7,
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};
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enum ClusterPlacement
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{
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PLACE_DB_CONSTR = 32,
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@@ -91,9 +91,10 @@ bool GateMateImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
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if (cell->belStrength != PlaceStrength::STRENGTH_FIXED && tile_extra_data(bel.tile)->die != preferred_die)
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return false;
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if (ctx->getBelType(bel).in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U)) {
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if (getBelBucketForCellType(ctx->getBelType(bel)) == id_CPE_FF) {
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Loc loc = ctx->getBelLocation(bel);
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const CellInfo *adj_half = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z == 3 ? 2 : 3)));
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const CellInfo *adj_half = ctx->getBoundBelCell(
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ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z == CPE_FF_L_Z ? CPE_FF_U_Z : CPE_FF_L_Z)));
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if (adj_half) {
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const auto &half_data = fast_cell_info.at(cell->flat_index);
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if (half_data.dff_used) {
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@@ -196,7 +197,7 @@ void GateMateImpl::postPlace()
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for (auto &cell : ctx->cells) {
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (l.z == 1) { // CPE_HALF_L
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if (l.z == CPE_LT_L_Z) {
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if (!cell.second->params.count(id_INIT_L20))
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cell.second->params[id_INIT_L20] = Property(0b1100, 4);
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}
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@@ -206,7 +207,7 @@ void GateMateImpl::postPlace()
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uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
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bool is_l2t5 = cell.second->type == id_CPE_L2T5_L;
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Loc loc = ctx->getBelLocation(bel);
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loc.z = 7; // CPE_LT_FULL
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loc.z = CPE_LT_FULL_Z;
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ctx->unbindBel(bel);
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ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength);
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cell.second->renamePort(id_IN1, id_IN5);
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@@ -251,7 +252,7 @@ void GateMateImpl::postPlace()
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}
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}
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loc.z = 0;
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loc.z = CPE_LT_U_Z;
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CellInfo *upper = ctx->getBoundBelCell(ctx->getBelByLocation(loc));
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if (upper->params.count(id_INIT_L00))
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cell.second->params[id_INIT_L00] = Property(int_or_default(upper->params, id_INIT_L00, 0), 4);
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