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mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-04-28 21:07:15 +00:00
This commit is contained in:
Miodrag Milanovic
2025-06-23 11:30:58 +02:00
parent 025af8b6d2
commit 31bceb02e9
3 changed files with 23 additions and 10 deletions

View File

@@ -257,7 +257,7 @@ struct BitstreamBackend
dict<IdString, Property> params = cell.second->params;
Loc l = ctx->getBelLocation(cell.second->bel);
if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
if (l.z == 0) {
if (l.z == CPE_LT_U_Z) {
update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
@@ -270,7 +270,7 @@ struct BitstreamBackend
update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
}
}
if (l.z == 7) {
if (l.z == CPE_LT_FULL_Z) {
if (cell.second->type.in(id_CPE_MX4)) {
update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params);
update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params);
@@ -305,7 +305,7 @@ struct BitstreamBackend
for (auto &p : params) {
IdString name = p.first;
switch (l.z) {
case 1: // CPE_LT_L
case CPE_LT_L_Z:
switch (p.first.index) {
case id_INIT_L00.index:
name = id_INIT_L02;
@@ -318,7 +318,7 @@ struct BitstreamBackend
break;
}
break;
case 4: // CPE_RAMIO_U
case CPE_RAMIO_U_Z:
switch (p.first.index) {
case id_C_RAM_I.index:
name = id_C_RAM_I2;
@@ -328,7 +328,7 @@ struct BitstreamBackend
break;
}
break;
case 5: // CPE_RAMIO_L
case CPE_RAMIO_L_Z:
switch (p.first.index) {
case id_C_RAM_I.index:
name = id_C_RAM_I1;

View File

@@ -85,6 +85,18 @@ enum CPEFunction
C_ADDCIN = 7,
};
enum CPE_Z
{
CPE_LT_U_Z = 0,
CPE_LT_L_Z = 1,
CPE_FF_U_Z = 2,
CPE_FF_L_Z = 3,
CPE_RAMIO_U_Z = 4,
CPE_RAMIO_L_Z = 5,
CPE_LINES_Z = 6,
CPE_LT_FULL_Z = 7,
};
enum ClusterPlacement
{
PLACE_DB_CONSTR = 32,

View File

@@ -91,9 +91,10 @@ bool GateMateImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
if (cell->belStrength != PlaceStrength::STRENGTH_FIXED && tile_extra_data(bel.tile)->die != preferred_die)
return false;
if (ctx->getBelType(bel).in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U)) {
if (getBelBucketForCellType(ctx->getBelType(bel)) == id_CPE_FF) {
Loc loc = ctx->getBelLocation(bel);
const CellInfo *adj_half = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z == 3 ? 2 : 3)));
const CellInfo *adj_half = ctx->getBoundBelCell(
ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z == CPE_FF_L_Z ? CPE_FF_U_Z : CPE_FF_L_Z)));
if (adj_half) {
const auto &half_data = fast_cell_info.at(cell->flat_index);
if (half_data.dff_used) {
@@ -196,7 +197,7 @@ void GateMateImpl::postPlace()
for (auto &cell : ctx->cells) {
if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
Loc l = ctx->getBelLocation(cell.second->bel);
if (l.z == 1) { // CPE_HALF_L
if (l.z == CPE_LT_L_Z) {
if (!cell.second->params.count(id_INIT_L20))
cell.second->params[id_INIT_L20] = Property(0b1100, 4);
}
@@ -206,7 +207,7 @@ void GateMateImpl::postPlace()
uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
bool is_l2t5 = cell.second->type == id_CPE_L2T5_L;
Loc loc = ctx->getBelLocation(bel);
loc.z = 7; // CPE_LT_FULL
loc.z = CPE_LT_FULL_Z;
ctx->unbindBel(bel);
ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength);
cell.second->renamePort(id_IN1, id_IN5);
@@ -251,7 +252,7 @@ void GateMateImpl::postPlace()
}
}
loc.z = 0;
loc.z = CPE_LT_U_Z;
CellInfo *upper = ctx->getBoundBelCell(ctx->getBelByLocation(loc));
if (upper->params.count(id_INIT_L00))
cell.second->params[id_INIT_L00] = Property(int_or_default(upper->params, id_INIT_L00, 0), 4);