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ecp5: Fix timing for DCU clock outputs

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Signed-off-by: gatecat <gatecat@ds0.me>
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gatecat
2026-04-15 09:24:33 +02:00
parent e6ecd8fab4
commit 4e9debe4e5
1 changed files with 2 additions and 0 deletions
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2
ecp5/arch.cc
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@@ -1015,6 +1015,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
} else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
return TMG_CLOCK_INPUT;
if (port.in(id_CH0_FF_TX_PCLK, id_CH0_FF_RX_PCLK, id_CH1_FF_TX_PCLK, id_CH1_FF_RX_PCLK))
return TMG_GEN_CLOCK;
std::string prefix = port.str(this).substr(0, 9);
if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
clockInfoCount = 1;