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Code Issues Releases Wiki Activity

Fixes

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This commit is contained in:
Miodrag Milanovic
2025-06-21 11:51:03 +02:00
parent d5bde28a7c
commit 9de539cd95
4 changed files with 46 additions and 52 deletions
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2
himbaechel/uarch/gatemate/gen/arch_gen.py
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@@ -239,7 +239,7 @@ def main():
pkg = ch.create_package(package)
for pad in sorted(dev.get_package_pads(package)):
pp = pkg.create_pad(pad.name, f"X{pad.x+2}Y{pad.y+2}", pad.bel, pad.function, pad.bank, pad.flags)
pp.extra_data = PadExtraData(pad.ddr.x+2, pad.ddr.y+2, pad.ddr.z)
pp.extra_data = PadExtraData(pad.ddr.x+2, pad.ddr.y+2, 4 if pad.ddr.z==0 else 5)
ch.write_bba(args.bba)

65
himbaechel/uarch/gatemate/pack.cc
View File

@@ -47,12 +47,12 @@ void GateMatePacker::disconnect_if_gnd(CellInfo *cell, IdString input)
}
}
CellInfo *GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc fixed)
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc)
{
CellInfo *cpe_half = nullptr;
CellInfo *cpe_ramio = nullptr;
NetInfo *net = cell->getPort(origPort);
if (net) {
Loc cpe_loc;
cpe_ramio = create_cell_ptr(id_CPE_RAMI, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), origPort.c_str(ctx)));
if (place) {
cell->constr_children.push_back(cpe_ramio);
@@ -60,7 +60,6 @@ CellInfo *GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool pla
cpe_ramio->constr_abs_z = false;
cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, origPort);
BelId b = ctx->getBelByLocation(cpe_loc);
ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED);
}
@@ -71,9 +70,7 @@ CellInfo *GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool pla
cpe_half->constr_abs_z = false;
cpe_half->constr_z = -4;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, origPort);
cpe_loc.z -= 4;
BelId b = ctx->getBelByLocation(cpe_loc);
BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4));
ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED);
}
@@ -84,23 +81,22 @@ CellInfo *GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool pla
cell->connectPort(origPort, ram_i);
cpe_ramio->connectPort(id_RAM_I, ram_i);
}
return cpe_ramio;
return std::make_pair(cpe_half, cpe_ramio);
}
CellInfo *GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc fixed)
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc)
{
CellInfo *cpe_half = nullptr;
CellInfo *cpe_ramio = nullptr;
NetInfo *net = cell->getPort(origPort);
Loc cpe_loc;
if (net) {
CellInfo *cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), origPort.c_str(ctx)));
cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), origPort.c_str(ctx)));
if (place) {
cell->constr_children.push_back(cpe_ramio);
cpe_ramio->cluster = cell->cluster;
cpe_ramio->constr_abs_z = false;
cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, origPort);
BelId b = ctx->getBelByLocation(cpe_loc);
ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED);
}
@@ -111,9 +107,7 @@ CellInfo *GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool pla
cpe_half->constr_abs_z = false;
cpe_half->constr_z = -4;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, origPort);
cpe_loc.z -= 4;
BelId b = ctx->getBelByLocation(cpe_loc);
BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4));
ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED);
}
if (net->name == ctx->id("$PACKER_GND")) {
@@ -137,29 +131,16 @@ CellInfo *GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool pla
cpe_half->connectPort(id_OUT, out);
cpe_ramio->connectPort(id_I, out);
}
return cpe_half;
return std::make_pair(cpe_half, cpe_ramio);
}
void GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed)
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place, Loc cpe_loc)
{
move_ram_i(cell, origPort, false, fixed);
}
CellInfo *GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed)
{
CellInfo *cpe = move_ram_o(cell, origPort, false, fixed);
return cpe;
}
CellInfo *GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place, Loc fixed)
{
CellInfo *cpe_half = nullptr;
NetInfo *i_net = cell->getPort(iPort);
NetInfo *o_net = cell->getPort(oPort);
if (!i_net && !o_net)
return cpe_half;
return std::make_pair(nullptr, nullptr);
Loc cpe_loc;
CellInfo *cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_cpe_ramio", cell->name.c_str(ctx), oPort.c_str(ctx)));
if (place) {
cell->constr_children.push_back(cpe_ramio);
@@ -167,20 +148,17 @@ CellInfo *GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString o
cpe_ramio->constr_abs_z = false;
cpe_ramio->constr_z = PLACE_DB_CONSTR + oPort.index;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, oPort);
BelId b = ctx->getBelByLocation(cpe_loc);
ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED);
}
cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe_half", cell->name.c_str(ctx), oPort.c_str(ctx)));
CellInfo *cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe_half", cell->name.c_str(ctx), oPort.c_str(ctx)));
if (place) {
cpe_ramio->constr_children.push_back(cpe_half);
cpe_half->cluster = cell->cluster;
cpe_half->constr_abs_z = false;
cpe_half->constr_z = -4;
} else {
cpe_loc = uarch->getRelativeConstraint(fixed, oPort);
cpe_loc.z -= 4;
BelId b = ctx->getBelByLocation(cpe_loc);
BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4));
ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED);
}
@@ -214,7 +192,22 @@ CellInfo *GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString o
cell->connectPort(iPort, ram_i);
cpe_ramio->connectPort(id_RAM_I, ram_i);
}
return cpe_half;
return std::make_pair(cpe_half, cpe_ramio);
}
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed)
{
return move_ram_i(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort));
}
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed)
{
return move_ram_o(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort));
}
std::pair<CellInfo*,CellInfo*> GateMatePacker::move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, Loc fixed)
{
return move_ram_io(cell, iPort, oPort, false, uarch->getRelativeConstraint(fixed, oPort));
}
void GateMatePacker::pack_misc()

11
himbaechel/uarch/gatemate/pack.h
View File

@@ -53,11 +53,12 @@ struct GateMatePacker
PllCfgRecord get_pll_settings(double f_ref, double f_core, int mode, int low_jitter, bool pdiv0_mux, bool feedback);
CellInfo *move_ram_i(CellInfo *cell, IdString origPort, bool place = true, Loc fixed = Loc());
CellInfo *move_ram_o(CellInfo *cell, IdString origPort, bool place = true, Loc fixed = Loc());
void move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed);
CellInfo *move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed);
CellInfo *move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place = true, Loc fixed = Loc());
std::pair<CellInfo*,CellInfo* >move_ram_i(CellInfo *cell, IdString origPort, bool place = true, Loc cpe_loc = Loc());
std::pair<CellInfo*,CellInfo*> move_ram_o(CellInfo *cell, IdString origPort, bool place = true, Loc cpe_loc = Loc());
std::pair<CellInfo*,CellInfo*> move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place = true, Loc cpe_loc = Loc());
std::pair<CellInfo*,CellInfo*> move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed);
std::pair<CellInfo*,CellInfo*> move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed);
std::pair<CellInfo*,CellInfo*> move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, Loc fixed);
uint8_t ram_ctrl_signal(CellInfo *cell, IdString port, bool alt);
uint8_t ram_clk_signal(CellInfo *cell, IdString port);
bool is_gpio_valid_dff(CellInfo *dff);

20
himbaechel/uarch/gatemate/pack_io.cc
View File

@@ -326,7 +326,10 @@ void GateMatePacker::pack_io_sel()
cells.push_back(&ci);
}
CellInfo *ddr[uarch->dies][9] = {nullptr}; // for each bank
std::pair<CellInfo*,CellInfo*> ddr[uarch->dies][9]; // for each bank
for (int i = 0; i < uarch->dies; ++i)
for (int j = 0; j < 9; ++j)
ddr[i][j] = {nullptr, nullptr};
auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
NetInfo *clk_net = cell->getPort(id_CLK);
@@ -477,21 +480,18 @@ void GateMatePacker::pack_io_sel()
oddr->movePortTo(id_D1, &ci, id_OUT1);
const auto &pad = ctx->get_package_pin(ctx->id(loc));
int die = uarch->tile_extra_data(ci.bel.tile)->die;
CellInfo *cpe_half = ddr[die][pad->pad_bank];
auto [cpe_half,cpe_ramio] = ddr[die][pad->pad_bank];
if (cpe_half) {
if (cpe_half->getPort(id_IN1) != oddr->getPort(id_DDR))
log_error("DDR port use signal different than already occupied DDR source.\n");
ci.ports[id_DDR].name = id_DDR;
ci.ports[id_DDR].type = PORT_IN;
ci.connectPort(id_DDR, cpe_half->getPort(id_RAM_O));
ci.connectPort(id_DDR, cpe_ramio->getPort(id_RAM_O));
} else {
oddr->movePortTo(id_DDR, &ci, id_DDR);
cpe_half = move_ram_o(&ci, id_DDR, false);
uarch->ddr_nets.insert(cpe_half->getPort(id_IN1)->name);
auto l = reinterpret_cast<const GateMatePadExtraDataPOD *>(pad->extra_data.get());
ctx->bindBel(ctx->getBelByLocation(Loc(l->x, l->y, l->z)), cpe_half,
PlaceStrength::STRENGTH_FIXED);
ddr[die][pad->pad_bank] = cpe_half;
oddr->movePortTo(id_DDR, &ci, id_DDR);
ddr[die][pad->pad_bank] = move_ram_o(&ci, id_DDR, false, Loc(l->x, l->y, l->z));
uarch->ddr_nets.insert(ddr[die][pad->pad_bank].first->getPort(id_IN1)->name);
}
use_custom_clock = set_out_clk(oddr, &ci);
bool invert = bool_or_default(oddr->params, id_CLK_INV, 0);
@@ -523,7 +523,7 @@ void GateMatePacker::pack_io_sel()
Loc root_loc = ctx->getBelLocation(ci.bel);
for (int i = 0; i < 4; i++) {
CellInfo *cpe = move_ram_o_fixed(&ci, ctx->idf("OUT%d", i + 1), root_loc);
CellInfo *cpe = move_ram_o_fixed(&ci, ctx->idf("OUT%d", i + 1), root_loc).first;
if (cpe && i == 2)
cpe->params[id_INIT_L10] = Property(0b0101, 4); // Invert CPE out for output enable (OUT3)
}