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https://github.com/YosysHQ/nextpnr.git
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Cleanups
This commit is contained in:
@@ -106,10 +106,8 @@ struct BitstreamBackend
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void update_cpe_mux(CellInfo *cell, IdString port, IdString param, int bit, dict<IdString, Property> ¶ms)
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{
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// Mux inversion data is contained in other CPE half
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Loc l = ctx->getBelLocation(cell->bel);
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CellInfo *cell_u = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(l.x, l.y, 0)));
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unsigned init_val = int_or_default(params, param);
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bool invert = need_inversion(cell_u, port);
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bool invert = need_inversion(cell, port);
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if (invert) {
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int old = (init_val >> bit) & 1;
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int val = (init_val & (~(1 << bit) & 0xf)) | ((!old) << bit);
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@@ -258,36 +256,41 @@ struct BitstreamBackend
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{
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// Update configuration bits based on signal inversion
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dict<IdString, Property> params = cell.second->params;
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uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (l.z==0 && func != C_MX4) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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if (l.z==0) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
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} else {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L03, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L03, params);
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}
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}
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if (l.z==1) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L03, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L03, params);
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if (func == C_MX4) {
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if (l.z==7) {
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if (cell.second->type.in(id_CPE_MX4)) {
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update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params);
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update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params);
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update_cpe_mux(cell.second.get(), id_IN3, id_INIT_L11, 2, params);
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update_cpe_mux(cell.second.get(), id_IN4, id_INIT_L11, 3, params);
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update_cpe_lt(cell.second.get(), id_IN5, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN6, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params);
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update_cpe_lt(cell.second.get(), id_IN8, id_INIT_L03, params);
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} else {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN5, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN6, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params);
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update_cpe_lt(cell.second.get(), id_IN8, id_INIT_L03, params);
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}
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}
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if (l.z==7) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params);
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update_cpe_lt(cell.second.get(), id_IN5, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN6, id_INIT_L02, params);
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update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params);
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update_cpe_lt(cell.second.get(), id_IN8, id_INIT_L03, params);
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}
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if (cell.second->type.in(id_CPE_FF)) {
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update_cpe_inv(cell.second.get(), id_CLK, id_C_CPE_CLK, params);
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@@ -34,10 +34,10 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
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cell->ports[id].type = dir;
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};
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if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_CI)) {
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add_port(id_I1, PORT_IN);
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add_port(id_I2, PORT_IN);
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add_port(id_I3, PORT_IN);
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add_port(id_I4, PORT_IN);
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add_port(id_IN1, PORT_IN);
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add_port(id_IN2, PORT_IN);
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add_port(id_IN3, PORT_IN);
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add_port(id_IN4, PORT_IN);
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add_port(id_OUT, PORT_OUT);
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if (type.in(id_CPE_LT_L, id_CPE_L2T5_L, id_CPE_CI)) {
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add_port(id_COUTY1, PORT_OUT);
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@@ -2235,4 +2235,4 @@ X(CPE_MX4)
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X(CPE_EN_CIN)
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X(CPE_CONCAT)
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X(CPE_ADDCIN)
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X(CPE_CI)
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X(CPE_CI)
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