mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-02-16 04:43:16 +00:00
Fix ADDF
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@@ -2042,7 +2042,6 @@ X(C_PY2_I)
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X(C_C_P)
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X(C_2D_IN)
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X(C_SN)
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X(C_O)
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X(C_O1)
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X(C_O2)
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X(C_BR)
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@@ -2059,8 +2058,6 @@ X(C_EN_SR)
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X(C_CLKSEL)
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X(C_ENSEL)
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X(FF_INIT)
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// Timing model for CPE
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X(CPE_DFF)
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// GPIO configuration parameters
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X(OPEN_DRAIN)
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@@ -131,8 +131,6 @@ void GateMatePacker::dff_to_cpe(CellInfo *dff)
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} else {
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dff->unsetParam(id_INIT);
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}
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//cpe->timing_index = ctx->get_cell_timing_idx(id_CPE_DFF);
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// cpe->params[id_C_O] = Property(0b00, 2);
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}
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void GateMatePacker::pack_cpe()
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@@ -151,11 +149,8 @@ void GateMatePacker::pack_cpe()
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ci.renamePort(id_I3, id_IN4);
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ci.renamePort(id_O, id_OUT);
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//ci.params[id_C_O] = Property(0b11, 2);
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ci.type = id_CPE_L2T5_L;
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} else if (ci.type == id_CC_MX2) {
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//ci.params[id_C_O] = Property(0b11, 2);
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ci.renamePort(id_D1, id_IN1);
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NetInfo *sel = ci.getPort(id_S0);
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ci.renamePort(id_S0, id_IN2);
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@@ -175,7 +170,6 @@ void GateMatePacker::pack_cpe()
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ci.renamePort(id_I2, id_IN3);
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ci.renamePort(id_I3, id_IN4);
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ci.renamePort(id_O, id_OUT);
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///ci.params[id_C_O] = Property(0b11, 2);
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if (ci.type.in(id_CC_LUT1, id_CC_LUT2)) {
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uint8_t val = int_or_default(ci.params, id_INIT, 0);
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if (ci.type == id_CC_LUT1)
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@@ -252,7 +246,6 @@ void GateMatePacker::pack_cpe()
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ci.params[id_INIT_L03] = Property(0b1100, 4); // IN8
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ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
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// ci.params[id_INIT_L20] = Property(0b1100, 4); // Always D1
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//ci.params[id_C_O] = Property(0b11, 2);
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ci.type = id_CPE_LT_L;
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", ci.name.c_str(ctx)));
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@@ -411,7 +404,8 @@ void GateMatePacker::pack_addf()
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ci_lower->cluster = root->name;
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ci_lower->constr_abs_z = false;
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ci_lower->constr_y = -1;
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//ci_lower->params[id_C_O] = Property(0b11, 2);
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// TODO: Need to check C_O1 handling in this case
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ci_lower->params[id_C_O1] = Property(0b11, 2);
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ci_lower->params[id_C_SELY1] = Property(1, 1);
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ci_lower->params[id_C_CY1_I] = Property(1, 1);
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ci_lower->params[id_INIT_L10] = Property(0b1010, 4); // D0
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@@ -478,7 +472,6 @@ void GateMatePacker::pack_addf()
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cy->params[id_INIT_L20] = Property(0b0110, 4); // XOR
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}
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cy->params[id_C_FUNCTION] = Property(merged ? C_ADDF2 : C_ADDF, 3);
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//cy->params[id_C_O] = Property(0b11, 2);
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cy->type = id_CPE_LT_L;
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", cy->name.c_str(ctx)));
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@@ -489,7 +482,6 @@ void GateMatePacker::pack_addf()
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upper->constr_z = -1;
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if (merged) {
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cy->movePortTo(id_S, upper, id_OUT);
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//upper->params[id_C_O] = Property(0b11, 2);
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} else {
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cy->renamePort(id_S, id_OUT);
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}
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@@ -534,7 +526,6 @@ void GateMatePacker::pack_addf()
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root->constr_children.push_back(co_lower);
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co_lower->constr_abs_z = false;
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co_lower->constr_y = +i + 1;
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//co_lower->params[id_C_O] = Property(0b11, 2);
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co_lower->params[id_C_FUNCTION] = Property(C_EN_CIN, 3);
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co_lower->params[id_INIT_L11] = Property(0b1100, 4);
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co_lower->params[id_INIT_L20] = Property(0b1100, 4);
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@@ -565,7 +556,6 @@ void GateMatePacker::pack_addf()
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break;
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}
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}
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//upper->params[id_C_O] = Property(0b10, 2);
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cy->movePortTo(id_CO, upper, id_OUT);
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}
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}
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