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https://github.com/YosysHQ/nextpnr.git
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Add lut tree tests for future improvements
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@@ -34,3 +34,94 @@ TEST_F(GateMateTest, pack_constants)
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packer.remove_constants();
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ASSERT_EQ(ctx->cells.size(), 0LU);
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}
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// LUT[1:0] Function
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// ==============================
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// 00 Constant 0
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// 01 NOT A (inverts input)
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// 10 A (passes input)
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// 11 Constant 1
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TEST_F(GateMateTest, remove_lut1_zero)
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{
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CellInfo *lut1 = create_cell_ptr(id_CC_LUT1, "lut");
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lut1->params[id_INIT] = Property(0b00, 2);
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CellInfo *obuf = create_cell_ptr(id_CC_OBUF, "obuf");
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direct_connect(lut1, id_O, obuf, id_A);
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ASSERT_EQ(ctx->cells.size(), 1LU);
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ctx->uarch->pack();
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ASSERT_EQ(ctx->cells.size(), 1LU);
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}
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TEST_F(GateMateTest, remove_lut1_one)
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{
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CellInfo *lut1 = create_cell_ptr(id_CC_LUT1, "lut");
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lut1->params[id_INIT] = Property(0b11, 2);
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CellInfo *obuf = create_cell_ptr(id_CC_OBUF, "obuf");
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direct_connect(lut1, id_O, obuf, id_A);
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ASSERT_EQ(ctx->cells.size(), 2LU);
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ctx->uarch->pack();
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ASSERT_EQ(ctx->cells.size(), 1LU);
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}
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TEST_F(GateMateTest, remove_lut1_pass)
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{
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CellInfo *lut1 = create_cell_ptr(id_CC_LUT1, "lut");
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lut1->params[id_INIT] = Property(0b10, 2);
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CellInfo *obuf = create_cell_ptr(id_CC_OBUF, "obuf");
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CellInfo *ibuf = create_cell_ptr(id_CC_IBUF, "ibuf");
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direct_connect(ibuf, id_Y, lut1, id_I0);
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direct_connect(lut1, id_O, obuf, id_A);
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ASSERT_EQ(ctx->cells.size(), 3LU);
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ctx->uarch->pack();
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// Expect IBUF -> CPE -> OBUF
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// LUT removed, but CPE for driving OBUF added
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ASSERT_EQ(ctx->cells.size(), 3LU);
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}
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TEST_F(GateMateTest, remove_lut1_inv)
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{
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CellInfo *lut1 = create_cell_ptr(id_CC_LUT1, "lut");
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lut1->params[id_INIT] = Property(0b01, 2);
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CellInfo *obuf = create_cell_ptr(id_CC_OBUF, "obuf");
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CellInfo *ibuf = create_cell_ptr(id_CC_IBUF, "ibuf");
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direct_connect(ibuf, id_Y, lut1, id_I0);
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direct_connect(lut1, id_O, obuf, id_A);
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ASSERT_EQ(ctx->cells.size(), 3LU);
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ctx->uarch->pack();
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// Expect IBUF -> CPE -> OBUF
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// LUT merged, but CPE for driving OBUF added
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ASSERT_EQ(ctx->cells.size(), 3LU);
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}
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TEST_F(GateMateTest, remove_lut1_not_driven)
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{
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CellInfo *lut1 = create_cell_ptr(id_CC_LUT1, "lut");
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lut1->params[id_INIT] = Property(0b01, 2);
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CellInfo *obuf = create_cell_ptr(id_CC_OBUF, "obuf");
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CellInfo *ibuf = create_cell_ptr(id_CC_IBUF, "ibuf");
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NetInfo *net_in = ctx->createNet(ctx->id("in"));
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ibuf->connectPort(id_Y, net_in);
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lut1->connectPort(id_I0, net_in);
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obuf->connectPort(id_A, net_in);
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ASSERT_EQ(ctx->cells.size(), 3LU);
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ctx->uarch->pack();
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// Expect IBUF -> CPE -> OBUF
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// LUT1 removed as not used, but CPE for driving OBUF added
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ASSERT_EQ(ctx->cells.size(), 3LU);
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}
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@@ -30,6 +30,7 @@ void GateMateTest::SetUp()
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{
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init_share_dirname();
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chipArgs.device = "CCGM1A1";
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chipArgs.options.emplace("allow-unconstrained", "");
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ctx = new Context(chipArgs);
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ctx->uarch->init(ctx);
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ctx->late_init();
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