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[ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE

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This commit is contained in:
Eddie Hung
2018-09-15 15:16:21 -07:00
parent e7fe046e57
commit c9059fc7d0
1 changed files with 13 additions and 6 deletions
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19
ice40/arch.cc
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@@ -866,15 +866,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
return TMG_COMB_INPUT; return TMG_COMB_INPUT;
if (port == id_COUT || port == id_LO) if (port == id_COUT || port == id_LO)
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
if (cell->lcInfo.dffEnable) { if (port == id_O) {
clockPort = id_CLK; // LCs with no inputs are constant drivers
if (port == id_O) if (cell->lcInfo.inputCount == 0)
return TMG_IGNORE;
if (cell->lcInfo.dffEnable) {
clockPort = id_CLK;
return TMG_REGISTER_OUTPUT; return TMG_REGISTER_OUTPUT;
}
else else
return TMG_REGISTER_INPUT;
} else {
if (port == id_O)
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
}
else {
if (cell->lcInfo.dffEnable) {
clockPort = id_CLK;
return TMG_REGISTER_INPUT;
}
else else
return TMG_COMB_INPUT; return TMG_COMB_INPUT;
} }