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gatemate: fix CI/CO RAM connections

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This commit is contained in:
Miodrag Milanovic 2025-08-25 12:24:46 +02:00
parent 84234e7d79
commit ca4f727ffc
1 changed files with 2 additions and 0 deletions
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2
himbaechel/uarch/gatemate/delay.cc
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@ -261,6 +261,8 @@ TimingPortClass GateMateImpl::getPortTimingClass(const CellInfo *cell, IdString
std::string name = port.str(ctx);
if (boost::starts_with(name, "CLKA[") || boost::starts_with(name, "CLKB[") || boost::starts_with(name, "CLOCK"))
return TMG_CLOCK_INPUT;
if (boost::ends_with(name, "_CI") || boost::ends_with(name, "_CO"))
return TMG_IGNORE;
if (name[0] == 'F') // Ignore forward and FIFO pins
return TMG_IGNORE;
for (auto c : boost::adaptors::reverse(name)) {