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himbaechel: gatemate: replace VLA with C++ features (#1513)

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José Miguel Sánchez García 2025-07-01 19:39:25 +02:00 committed by GitHub
parent 27635785c8
commit cb9f3117ba
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3 changed files with 3 additions and 3 deletions
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2
himbaechel/uarch/gatemate/bitstream.cc
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@ -223,7 +223,7 @@ struct BitstreamBackend
{
ChipConfig cc;
cc.chip_name = device;
int bank[uarch->dies][9] = {0};
std::vector<std::array<int, 9>> bank(uarch->dies);
for (auto &cell : ctx->cells) {
CfgLoc loc = get_config_loc(cell.second.get()->bel.tile);
auto &params = cell.second.get()->params;

2
himbaechel/uarch/gatemate/pack_clocking.cc
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@ -329,7 +329,7 @@ void GateMatePacker::remove_clocking()
void GateMatePacker::pack_pll()
{
int pll_index[uarch->dies] = {0};
std::vector<int> pll_index(uarch->dies);
log_info("Packing PLLss..\n");
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;

2
himbaechel/uarch/gatemate/pack_io.cc
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@ -326,7 +326,7 @@ void GateMatePacker::pack_io_sel()
cells.push_back(&ci);
}
CellInfo *ddr[uarch->dies][9] = {nullptr}; // for each bank
std::vector<std::array<CellInfo *, 9>> ddr(uarch->dies); // for each bank
auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
NetInfo *clk_net = cell->getPort(id_CLK);