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ecp5: Fix timing pip classes

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
2018-11-15 17:39:13 +00:00
parent 3ecd440748
commit cc746d888b
1 changed files with 1 additions and 1 deletions
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ecp5/trellis_import.py
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@@ -222,7 +222,7 @@ def write_database(dev_name, chip, ddrg, endianness):
loc = loc_with_type[arc_loctype]
lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)]
wire = ddrg.locationTypes[lt].wires[idx]
return "R{}C{}_{}".format(loc[0] + rel.x, loc[1] + rel.y, ddrg.to_str(wire.name))
return "R{}C{}_{}".format(loc[1] + rel.y, loc[0] + rel.x, ddrg.to_str(wire.name))
bba = BinaryBlobAssembler()
bba.pre('#include "nextpnr.h"')