POSIX allows any `int` value to be returned but specifies that only
the low 8 bits are available in some contexts:
https://pubs.opengroup.org/onlinepubs/9699919799/functions/_exit.html
For reasons that aren't entirely clear, WASI requires the value to be
in range [0;126), and this is enforced with an assertion at runtime
level in Wasmtime. This should probably be fixed in Wasmtime but until
it is done there doesn't seem to be any harm in returning `125` instead
of `-1`. This also removes any discrepancy due to truncation.
* generic: Fix Python path not including the examples/ directory in the example
It seems that at some point, the embedded Python stopped including the
directory that nextpnr-generic was executed in inside of its sys.path.
This likely happened by de3d5be8 specifying an explicit argv to
the interpreter init function.
* generic: Improve the example for K != 4
Configuring K < 4 used to result in "dangling" inputs to the cells being
generated (those are just not driven by anything in the resulting Verilog/JSON).
Configuring K > 4 used to result in an assertion crash in cells.cc.
The ctx.setLutK call fixes both cases.
Define open_(o|i)fstream_and_log_error in log.h to:
- quote 'filename'
- add error cause to easier troubleshoot
- use existing consistent string style
- easily allows OS specific message
Introduce it when file are opened and add it where error message
was missing.
* gatemate: removing recursion in GateMateImpl::reassign_bridges
* gatemate: improving comments in GateMateImpl:reassign_bridges
* gatemate: making naming more consistent, adding comments about the need for recursion removal
Add CLKDIV — a frequency divider with ratios of 1, 2, 3, 3.5, 4,
5, 6, 7, and 8.
A direct, non-switchable connection to CLKDIV2 makes placement more
difficult — we have to account for CLKDIV2’s occupancy for IOLOGIC and,
if necessary, duplicate the cell, as well as create clusters of CLKDIV
and CLKDIV2.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* nix: fix issue with latest apycula being needed and it not being in Nixpkgs stable
* nix: we really should be using the latest version unless a regression happens tbh
* Gowin. Implement GW5A HCLK and CLKDIV2.
HCLK pins have been added for the GW5A series, and the placement of
CLKDIV2 primitives has been updated to account for the specific
characteristics of this chip series.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
* Gowin. Fix style.
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This fixes a memory issue. When you assign to base_iodelay_rules from itself, the LHS when you do `base_iodelay_rules[id_DELAYA] = base_iodelay_rules[id_DELAYB]`, can cause a heap allocation which possibly invalidates the memory of the RHS.
This was found while running nextpnr under ASAN. It might be useful to add testing under libasan into CI.
