Added support for "keep" attribute to abc pass
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@@ -447,7 +447,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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extract_cell(c);
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for (auto &wire_it : module->wires) {
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if (wire_it.second->port_id > 0)
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if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
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mark_port(RTLIL::SigSpec(wire_it.second));
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}
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