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abc9_ops: -reintegrate to use derived_type for box_ports

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This commit is contained in:
Eddie Hung
2020-02-05 14:46:48 -08:00
parent 5ebdc0f8e0
commit 0b308c6835
2 changed files with 23 additions and 3 deletions
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2
passes/techmap/abc9_ops.cc
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@@ -797,7 +797,7 @@ void reintegrate(RTLIL::Module *module)
}
int input_count = 0, output_count = 0;
for (const auto &port_name : box_ports.at(cell->type)) {
for (const auto &port_name : box_ports.at(derived_type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);

24
tests/arch/xilinx/dffs.ys
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@@ -8,7 +8,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
@@ -20,6 +19,27 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D