abc9_ops: -reintegrate to use derived_type for box_ports
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@@ -797,7 +797,7 @@ void reintegrate(RTLIL::Module *module)
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}
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int input_count = 0, output_count = 0;
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for (const auto &port_name : box_ports.at(cell->type)) {
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for (const auto &port_name : box_ports.at(derived_type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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