FDCE_1 does not have IS_CLR_INVERTED

2026-01-28 21:11:14 +00:00 · 2019-09-29 11:25:34 -07:00
parent 5a4011e8c9
commit 18ebb86edb
1 changed files with 1 additions and 1 deletions
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -408,7 +408,7 @@ module FDCE_1 (
  always @* Q = \$nextQ ;
 `else
  assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule