fixup verilog doubleslash test

- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again

tests/verilog/.gitignore

@@ -3,3 +3,4 @@
 /run-test.mk
 /const_arst.v
 /const_sr.v
+/doubleslash.v

tests/verilog/doubleslash.ys

@@ -17,3 +17,5 @@ proc
 opt -full
 
 write_verilog doubleslash.v
+design -reset
+read_verilog doubleslash.v