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Merge pull request #3263 from YosysHQ/micko/clk2ff_init

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Set init values for wrapped  async control signals
This commit is contained in:
Miodrag Milanović
2022-04-01 19:37:02 +02:00
committed by GitHub
parent 2ec4af56e6 86ce441af6
commit 2a76af9eb6
1 changed files with 2 additions and 0 deletions
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2
passes/sat/clk2fflogic.cc
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@@ -44,6 +44,7 @@ struct Clk2fflogicPass : public Pass {
}
SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
Wire *past_sig = module->addWire(past_sig_id, GetSize(sig));
past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
module->addFf(NEW_ID, sig, past_sig);
if (polarity)
sig = module->Or(NEW_ID, sig, past_sig);
@@ -56,6 +57,7 @@ struct Clk2fflogicPass : public Pass {
}
SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) {
Wire *past_sig = module->addWire(NEW_ID);
past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
module->addFfGate(NEW_ID, sig, past_sig);
if (polarity)
sig = module->OrGate(NEW_ID, sig, past_sig);