opt_expr: fix invert_map
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@@ -401,7 +401,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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auto dirty_cells = module->dirty_cells(timestamp);
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for (auto cell : dirty_cells) {
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// TODO this could be cheaper
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for (auto cell : module->cells()) {
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if (design->selected(module, cell) && cell->type[0] == '$') {
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if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
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GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
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