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Code Issues Releases Wiki Activity

newcelltypes: TurboCellTypes -> StaticCellTypes

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This commit is contained in:
Emil J. Tywoniak
2025-11-25 16:11:05 +01:00
parent 6adc08b0e5
commit 35ccaa60d7
3 changed files with 6 additions and 6 deletions
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2
kernel/newcelltypes.h
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@@ -5,7 +5,7 @@
YOSYS_NAMESPACE_BEGIN
namespace TurboCellTypes {
namespace StaticCellTypes {
constexpr int MAX_CELLS = 300;
constexpr int MAX_PORTS = 10;

8
passes/opt/opt_clean.cc
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@@ -102,9 +102,9 @@ struct keep_cache_t
};
keep_cache_t keep_cache;
static constexpr auto ct_reg = TurboCellTypes::Categories::join(
TurboCellTypes::Compat::internals_mem_ff,
TurboCellTypes::categories.is_anyinit);
static constexpr auto ct_reg = StaticCellTypes::Categories::join(
StaticCellTypes::Compat::mem_ff,
StaticCellTypes::categories.is_anyinit);
CellTypes ct_all;
int count_rm_cells, count_rm_wires;
@@ -526,7 +526,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
dict<SigBit, State> qbits;
for (auto cell : module->cells())
if (TurboCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
{
SigSpec sig = cell->getPort(ID::Q);

2
passes/opt/opt_expr.cc
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@@ -431,7 +431,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
if (!TurboCellTypes::Compat::stdcells_mem(cell->type))
if (!StaticCellTypes::Compat::stdcells_mem(cell->type))
continue;
handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);