Do not assume inst_module is always present
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@@ -193,12 +193,13 @@ struct XAigerWriter
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continue;
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}
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log_assert(inst_module);
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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if (inst_module) {
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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if (inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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if (inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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}
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}
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if (cell->input(conn.first)) {
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@@ -254,7 +255,6 @@ struct XAigerWriter
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// continue;
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//}
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log_assert(inst_module);
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if (inst_flop) {
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SigBit d, q;
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for (const auto &c : cell->connections()) {
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@@ -279,7 +279,7 @@ struct XAigerWriter
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ff_bits.emplace_back(d, q);
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undriven_bits.erase(q);
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}
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else if (!inst_module->attributes.count("\\abc_box_id")) {
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else if (inst_module && !inst_module->attributes.count("\\abc_box_id")) {
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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for (auto b : c.second.bits()) {
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@@ -386,15 +386,12 @@ struct XAigerWriter
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}
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// Do some CI/CO post-processing:
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// Erase all POs and COs that are undriven
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for (auto bit : undriven_bits) {
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//co_bits.erase(bit);
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// Erase all POs that are undriven
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for (auto bit : undriven_bits)
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output_bits.erase(bit);
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}
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// CIs cannot be undriven
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for (const auto &c : ci_bits)
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undriven_bits.erase(c.first);
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for (auto bit : unused_bits)
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undriven_bits.erase(bit);
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