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Merge pull request #953 from YosysHQ/clifford/fix948

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Add support for zero-width signals to Verilog back-end
This commit is contained in:
Clifford Wolf
2019-04-22 20:01:09 +02:00
committed by GitHub
parent 9050b5e191 0e0c80fac8
commit 3be5aac52c
1 changed files with 8 additions and 0 deletions
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8
backends/verilog/verilog_backend.cc
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@@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
{
if (width < 0)
width = data.bits.size() - offset;
if (width == 0) {
f << "\"\"";
return;
}
if (nostr)
goto dump_hex;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
@@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
{
if (GetSize(sig) == 0) {
f << "\"\"";
return;
}
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {