github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-06 16:54:36 +00:00
Code Issues Releases Wiki Activity

Read init from outputs

Browse Source
This commit is contained in:
Eddie Hung
2019-06-15 22:41:42 -07:00
parent d969a9060e
commit 3d1185b835
1 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/aiger/aigerparse.cc
View File

@@ -927,6 +927,10 @@ void AigerReader::post_process()
}
}
log_debug(" -> %s\n", log_id(wire));
int init;
mf >> init;
if (init < 2)
wire->attributes["\\init"] = init;
}
else if (type == "box") {
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));