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Revert "Fold loop"

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This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.
This commit is contained in:
Eddie Hung 2019-11-27 12:35:25 -08:00
parent 4bac6b13be
commit 403214f44d
1 changed files with 6 additions and 3 deletions
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9
backends/aiger/xaiger.cc
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@ -184,7 +184,6 @@ struct XAigerWriter
if (bit != wirebit)
alias_map[bit] = wirebit;
input_bits.insert(wirebit);
undriven_bits.erase(bit);
}
if (wire->port_output || keep) {
@ -192,8 +191,6 @@ struct XAigerWriter
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
if (!wire->port_input)
unused_bits.erase(bit);
}
else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@ -201,6 +198,12 @@ struct XAigerWriter
}
}
for (auto bit : input_bits)
undriven_bits.erase(sigmap(bit));
for (auto bit : output_bits)
if (!bit.wire->port_input)
unused_bits.erase(bit);
// TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users;