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mirror of synced 2026-02-11 02:49:49 +00:00

proc_dff: better error context

This commit is contained in:
Emil J. Tywoniak
2026-02-09 19:02:51 +01:00
parent 383daa1eb3
commit 404ce980e4

View File

@@ -157,6 +157,20 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
log(".\n");
}
template <typename T>
static void error_at_src(const RTLIL::Const* src, T msg) {
if (!src || src->empty()) {
log_error("%s\n", msg);
} else {
log_error("%s: %s\n", src->decode_string(), msg);
}
}
template <typename T>
static void error_at_proc(const RTLIL::Process* proc, T msg) {
error_at_src(proc->attributes.count(ID::src) ? &proc->attributes.at(ID::src) : nullptr, msg);
}
void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{
while (1)
@@ -194,14 +208,15 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
async_rules.emplace_back(rstval, sync);
}
else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
if (sync_edge != NULL && sync_edge != sync)
log_error("Multiple edge sensitive events found for this signal!\n");
if (sync_edge != NULL && sync_edge != sync) {
error_at_src(&action.src, stringf("Multiple edge sensitive events found for signal %s", log_signal(sig)));
}
sig.replace(action.lhs, action.rhs, &insig);
sync_edge = sync;
}
else if (sync->type == RTLIL::SyncType::STa) {
if (sync_always != NULL && sync_always != sync)
log_error("Multiple always events found for this signal!\n");
error_at_proc(proc, stringf("Multiple always events found for signal %s", log_signal(sig)));
sig.replace(action.lhs, action.rhs, &insig);
sync_always = sync;
}
@@ -210,7 +225,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
global_clock = true;
}
else {
log_error("Event with any-edge sensitivity found for this signal!\n");
error_at_proc(proc, stringf("Event with any-edge sensitivity found for signal %s", log_signal(sig)));
}
action.lhs.remove2(sig, &action.rhs);
@@ -262,14 +277,14 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (sync_always) {
if (sync_edge || !async_rules.empty())
log_error("Mixed always event with edge and/or level sensitive events!\n");
error_at_proc(proc, stringf("Mixed always event with edge and/or level sensitive events for signal %s", log_signal(sig)));
log(" created direct connection (no actual register cell created).\n");
mod->connect(RTLIL::SigSig(sig, insig));
continue;
}
if (!sync_edge && !global_clock)
log_error("Missing edge-sensitive event for this signal!\n");
error_at_proc(proc, stringf("Missing edge-sensitive event for signal %s", log_signal(sig)));
// More than one reset value so we derive a dffsr formulation
if (async_rules.size() > 1)