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Merge pull request #5346 from YosysHQ/emil/verilog-codeowner

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CODEOWNERS: add myself for read_verilog and AST
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Emil J
2025-09-15 17:38:00 +02:00
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parent 7d82d80a95 1c422fcb6e
commit 475d455698
1 changed files with 2 additions and 2 deletions
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@@ -30,8 +30,8 @@ docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty
# These still override previous lines, so be careful not to
# accidentally disable any of the above rules.
frontends/verilog/ @zachjs
frontends/ast/ @zachjs
frontends/verilog/ @widlarizer
frontends/ast/ @widlarizer
techlibs/intel_alm/ @Ravenslofty
techlibs/gowin/ @pepijndevos