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Merge pull request #1072 from YosysHQ/eddie/fix_1069

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Error out if no top module given before 'sim'
This commit is contained in:
Clifford Wolf
2019-06-06 06:49:07 +02:00
committed by GitHub
parent fd8ef128bf dd134914cc
commit 50e2dce5e7
1 changed files with 5 additions and 0 deletions
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5
passes/sat/sim.cc
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@@ -88,6 +88,8 @@ struct SimInstance
SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
{
log_assert(module);
if (parent) {
log_assert(parent->children.count(instance) == 0);
parent->children[instance] = this;
@@ -848,6 +850,9 @@ struct SimPass : public Pass {
if (design->full_selection()) {
top_mod = design->top_module();
if (!top_mod)
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_whole_modules();
if (GetSize(mods) != 1)