github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-27 12:43:21 +00:00
Code Issues Releases Wiki Activity

read_verilog cells_box.v before techmap

Browse Source
This commit is contained in:
Eddie Hung
2019-04-16 12:41:56 -07:00
parent d259e6dc14
commit 5189695362
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/xilinx/synth_xilinx.cc
View File

@@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v");
Pass::call(design, "read_verilog +/xilinx/cells_box.v");
Pass::call(design, "techmap -map +/techmap.v");
if (abc == "abc9")
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
else