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Merge pull request #3733 from AdamHillier/aiger-inputs

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Add outputs before inputs to the sigmap in the AIGER backend.
This commit is contained in:
Jannis Harder
2023-05-22 16:09:15 +02:00
committed by GitHub
parent 890849447f 3861cc31f0
commit 5fb1223861
1 changed files with 5 additions and 5 deletions
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10
backends/aiger/aiger.cc
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@@ -119,16 +119,16 @@ struct AigerWriter
if (wire->name.isPublic())
sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
// promote output wires
for (auto wire : module->wires())
if (wire->port_output)
sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
for (auto wire : module->wires())
{
if (wire->attributes.count(ID::init)) {