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docs: restore and update the note about if/case attributes.

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Gary Wong
2025-05-30 21:13:20 -06:00
parent 7b09dc31af
commit 62660b221f
1 changed files with 4 additions and 1 deletions
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docs/source/yosys_internals/verilog.rst
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@@ -377,4 +377,7 @@ from SystemVerilog:
- Assignments within expressions are supported.
- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
supported on ``if`` and ``case`` conditionals.
supported on ``if`` and ``case`` conditionals. (The Verilog frontend
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)