github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-25 11:56:22 +00:00
Code Issues Releases Wiki Activity

Merge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotes

Browse Source 
readme: Fix formatting of a keyword
This commit is contained in:
Clifford Wolf 2018-08-06 10:41:53 +02:00 committed by GitHub
commit 63f4cc38eb
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -389,7 +389,7 @@ Verilog Attributes and non-standard features
Non-standard or SystemVerilog features for formal verification
==============================================================
- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled
- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
when ``read_verilog`` is called with ``-formal``.
- The system task ``$initstate`` evaluates to 1 in the initial state and