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Merge pull request #1036 from YosysHQ/eddie/xilinx_dram

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Add "min bits" and "min wports" to xilinx dram rules
This commit is contained in:
Eddie Hung
2019-05-23 13:13:10 -07:00
committed by GitHub
parent ca46947354 99a3fee8f4
commit 67a4850e35
1 changed files with 4 additions and 0 deletions
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4
techlibs/xilinx/drams.txt
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@@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D
endbram
match $__XILINX_RAM64X1D
min bits 5
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
min bits 9
min wports 1
make_outreg
endmatch