Added support for "always @(*)"

README

@@ -74,7 +74,7 @@ or using a simple synthesis script:
 	proc; opt; techmap; opt
 	write_verilog synth.v
 
-	$ ././yosys synth.ys
+	$ ./yosys synth.ys
 
 It is also possible to only have the synthesis commands but not the read/write
 commands in the synthesis script:

frontends/verilog/parser.y

@@ -616,6 +616,9 @@ always_stmt:
 
 always_cond:
 	'@' '(' always_events ')' |
+	'@' '(' '*' ')' |
+	'@' ATTR_BEGIN ')' |
+	'@' '(' ATTR_END |
 	'@' '*' |
 	/* empty */;