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mirror of synced 2026-05-23 13:46:47 +00:00
Code Issues Releases Wiki Activity

signorm: safer indexing if broken invariant

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This commit is contained in:
Emil J. Tywoniak
2026-05-22 17:21:40 +02:00
parent dcc68e49fb
commit 72b60b6cef
1 changed files with 28 additions and 24 deletions
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52
kernel/rtlil_bufnorm.cc
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@@ -149,9 +149,11 @@ struct RTLIL::SigNormIndex
if (cell->port_dir(port) != RTLIL::PD_INPUT)
continue;
int i = 0;
for (auto bit : sig)
for (auto bit : sig) {
if (bit.is_wire())
fanout[bit].insert(PortBit(cell, port, i++));
fanout[bit].insert(PortBit(cell, port, i));
i++;
}
}
}
}
@@ -995,17 +997,17 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
bool is_input_port = port_dir(portname) == RTLIL::PD_INPUT;
if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
int i = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())
fanout.erase(found);
if (bit.is_wire()) {
auto found = fanout.find(bit);
log_assert(found != fanout.end());
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())
fanout.erase(found);
}
i++;
}
} else if (GetSize(conn_it->second)) {
Wire *w = conn_it->second.as_wire();
@@ -1129,17 +1131,17 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
if (!r.second) {
if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
int i = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())
fanout.erase(found);
if (bit.is_wire()) {
auto found = fanout.find(bit);
log_assert(found != fanout.end());
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())
fanout.erase(found);
}
i++;
}
} else {
Wire *w = conn_it->second.as_wire();
@@ -1153,9 +1155,11 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout;
int i = 0;
for (auto bit : signal)
for (auto bit : signal) {
if (bit.is_wire())
fanout[bit].insert(PortBit(this, portname, i++));
fanout[bit].insert(PortBit(this, portname, i));
i++;
}
} else if (GetSize(signal)) {
Wire *w = signal.as_wire();
log_assert(w->driverCell_ == nullptr);