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greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency

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This commit is contained in:
Andrew Zonenberg
2016-12-10 13:57:37 +08:00
parent 8767cdcac9
commit 797c03997e
1 changed files with 15 additions and 15 deletions
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30
techlibs/greenpak4/cells_sim.v
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@@ -249,12 +249,12 @@ module GP_DLATCH(input D, input nCLK, output reg Q);
end
endmodule
module GP_DLATCHI(input D, input nCLK, output reg Q);
module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
Q <= ~D;
nQ <= ~D;
end
endmodule
@@ -269,14 +269,14 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
end
endmodule
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q);
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b1;
nQ <= 1'b1;
else if(!nCLK)
Q <= ~D;
nQ <= ~D;
end
endmodule
@@ -291,14 +291,14 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
end
endmodule
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q);
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b0;
nQ <= 1'b0;
else if(!nCLK)
Q <= ~D;
nQ <= ~D;
end
endmodule
@@ -314,15 +314,15 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
end
endmodule
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q);
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(*) begin
if(!nSR)
Q <= ~SRMODE;
nQ <= ~SRMODE;
else if(!nCLK)
Q <= ~D;
nQ <= ~D;
end
endmodule