github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-27 01:10:41 +00:00
Code Issues Releases Wiki Activity

verilog_parser: silence yynerrs warning

Browse Source
This commit is contained in:
Emil J. Tywoniak
2024-10-15 12:16:02 +02:00
committed by Zachary Snow
parent adb6cdb167
commit 81bbde62ca
1 changed files with 1 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
frontends/verilog/verilog_parser.y
View File

@@ -464,6 +464,7 @@ static const AstNode *addAsgnBinopStmt(dict<IdString, AstNode*> *attr, AstNode *
%%
input: {
(void)frontend_verilog_yynerrs;
ast_stack.clear();
ast_stack.push_back(current_ast);
} design {