github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-16 01:51:02 +00:00
Code Issues Releases Wiki Activity

rtlil_bufnorm: more xlog

Browse Source
This commit is contained in:
Emil J. Tywoniak
2026-04-07 19:30:19 +02:00
parent 42e01aa1ca
commit 8798b15fa0
1 changed files with 5 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
kernel/rtlil_bufnorm.cc
View File

@@ -30,7 +30,9 @@ YOSYS_NAMESPACE_BEGIN
typedef std::pair<Cell*, IdString> cell_port_t;
// Since this is kernel code, we only log with yosys_xtrace set to not get
// in the way when using `debug` to debug specific passes.q
#define xlog(...) do { if (yosys_xtrace) log("#X [bufnorm] " __VA_ARGS__); } while (0)
struct RTLIL::SigNormIndex
{
@@ -315,6 +317,7 @@ void RTLIL::Design::sigNormalize(bool enable)
return;
xlog("leaving signorm\n");
for (auto module : modules()) {
module->connections();
if (module->sig_norm_index != nullptr) {
@@ -343,8 +346,7 @@ void RTLIL::Design::sigNormalize(bool enable)
if (!flagSigNormalized)
{
xlog("entering signorm\n");
flagSigNormalized = true;
}
@@ -507,9 +509,6 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
void RTLIL::Module::bufNormalize()
{
// Since this is kernel code, we only log with yosys_xtrace set to not get
// in the way when using `debug` to debug specific passes.q
#define xlog(...) do { if (yosys_xtrace) log("#X [bufnorm] " __VA_ARGS__); } while (0)
if (!design->flagBufferedNormalized)
return;