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quicklogic: Avoid carry chains in division mapping

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The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
This commit is contained in:
Martin Povišer
2024-09-19 11:21:09 +02:00
parent 4d581a97d6
commit 9018d06a33
2 changed files with 4 additions and 2 deletions
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3
techlibs/common/techmap.v
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@@ -304,6 +304,7 @@ endmodule
// Divide and Modulo
// --------------------------------------------------------
`ifndef NODIV
module \$__div_mod_u (A, B, Y, R);
parameter WIDTH = 1;
@@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y);
.R(Y)
);
endmodule
`endif
// --------------------------------------------------------
// Power

3
techlibs/quicklogic/synth_quicklogic.cc
View File

@@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_gates")) {
if (inferAdder && family == "qlf_k6n10f") {
run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)");
run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)");
run("techmap", "(unless -no_adder)");
} else {
run("techmap");
}