github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-02 07:01:06 +00:00
Code Issues Releases Wiki Activity

Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor

Browse Source
This commit is contained in:
Eddie Hung
2019-08-28 10:51:39 -07:00
parent 13424352cc
commit 9314a0a42e
1 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
techlibs/xilinx/cells_sim.v
View File

@@ -380,9 +380,10 @@ endmodule
module SRL16E (
output Q,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
input CLK,
input A0, A1, A2, A3, CE, D
input D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -401,7 +402,10 @@ endmodule
module SRLC16E (
output Q,
output Q15,
input A0, A1, A2, A3, CE, CLK, D
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
input CLK,
input D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -422,9 +426,10 @@ module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE,
(* clkbuf_sink *)
input CLK,
input CE, D
input D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;