Typo

2026-05-04 07:10:19 +00:00 · 2019-08-20 17:51:50 -07:00
parent 8f666ebac1
commit 96f00e9147
1 changed files with 1 additions and 1 deletions
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -165,7 +165,7 @@ module RAM64X1D (
  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
 endmodule

-module \$__ABC_RAM128X1D (
+module RAM128X1D (
  output       DPO, SPO,
  input        D,
  input        WCLK,