synth_gatemate: Apply new test practice with assert-max

tests/arch/gatemate/add_sub.ys

@@ -5,5 +5,5 @@ equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivale
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:CC_ADDF
-select -assert-count 4 t:CC_LUT1
+select -assert-max 4 t:CC_LUT1
 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D

tests/arch/gatemate/adffs.ys

@@ -28,7 +28,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
 
 design -load read
@@ -39,5 +39,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D

tests/arch/gatemate/fsm.ys

@@ -14,7 +14,7 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:CC_BUFG
 select -assert-count 6 t:CC_DFF
-select -assert-count 4 t:CC_LUT2
-select -assert-count 2 t:CC_LUT3
-select -assert-count 8 t:CC_LUT4
+select -assert-max 5 t:CC_LUT2
+select -assert-max 4 t:CC_LUT3
+select -assert-max 9 t:CC_LUT4
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

tests/arch/gatemate/latches.ys

@@ -25,5 +25,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_DLT
-select -assert-count 2 t:CC_LUT3
+select -assert-max 2 t:CC_LUT3
 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D

tests/arch/gatemate/logic.ys

@@ -4,7 +4,7 @@ proc
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_LUT1
-select -assert-count 6 t:CC_LUT2
-select -assert-count 2 t:CC_LUT4
+select -assert-max 1 t:CC_LUT1
+select -assert-max 6 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D

tests/arch/gatemate/mul.ys

@@ -28,6 +28,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd mul_unsigned_sync # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_MULT
 select -assert-count 1 t:CC_BUFG
-select -assert-count 18 t:CC_LUT4
+select -assert-max 18 t:CC_LUT4
 select -assert-count 18 t:CC_DFF
 select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D

tests/arch/gatemate/tribuf.ys

@@ -8,6 +8,6 @@ equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate #
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 2 t:CC_IBUF
-select -assert-count 1 t:CC_LUT1
+select -assert-max 1 t:CC_LUT1
 select -assert-count 1 t:CC_TOBUF
 select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D