Test empty switches

tests/proc/bug5572.ys

@@ -0,0 +1,19 @@
+read_rtlil << EOT
+attribute \top 1
+module \top
+  wire width 1 \sig
+  wire width 1 \val
+
+  process $2
+    switch \sig [0]
+      case 1'0
+      case 1'1
+      case
+        assign \val [0] 1'1
+    end
+  end
+end
+EOT
+proc_rmdead
+proc_clean
+select -assert-none p:*

tests/verilog/.gitignore

@@ -1,3 +1,4 @@
+/bug5572.v
 /const_arst.v
 /const_sr.v
 /doubleslash.v

tests/verilog/bug5572.ys

@@ -0,0 +1,15 @@
+read_rtlil << EOT
+module \top
+  wire \sig
+  wire \val
+  process $2
+    attribute \full_case 1
+    switch \sig
+    end
+  end
+end
+EOT
+
+write_verilog bug5572.v
+design -reset
+read_verilog bug5572.v