Fix in sincos testbench gen

2026-04-25 11:52:05 +00:00 · 2013-12-04 09:24:52 +01:00
parent d1517b7982
commit a2d053694b
1 changed files with 1 additions and 1 deletions
--- a/tests/simple/sincos.v
+++ b/tests/simple/sincos.v
@@ -39,7 +39,7 @@ input start;
 input clock;
 input reset;

-(* gentb_constant="0" *)
+(* gentb_constant = 1'b0 *)
 wire reset;

 always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR