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mirror of synced 2026-02-14 12:14:03 +00:00

tests: check shifts by amounts that overflow int

This commit is contained in:
George Rennie
2025-05-07 15:12:33 +02:00
parent 0dcd94b6ad
commit af933b4f38

View File

@@ -48,3 +48,25 @@ select -assert-none t:$shl
select -assert-none t:$shr
select -assert-none t:$sshl
select -assert-none t:$sshr
design -reset
read_verilog <<EOT
module top (in, out1, out2);
input wire in;
output wire [7:0] out1;
output wire [7:0] out2;
assign out1 = (in >> 36'hfffffffff);
wire signed [35:0] shamt = 36'hfffffffff;
assign out2 = (in >> shamt);
endmodule
EOT
equiv_opt opt_expr
design -load postopt
select -assert-none t:$shl
select -assert-none t:$shr
select -assert-none t:$sshl
select -assert-none t:$sshr