verilog: fix wildcard port connections leaking memory

2026-04-13 17:08:00 +00:00 · 2021-03-18 10:38:36 +01:00
parent 62a42c317c
commit b57e47fad8
1 changed files with 1 additions and 0 deletions
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2084,6 +2084,7 @@ cell_port:
 		if (!sv_mode)
 			frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
 		astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
+		free_attr($1);
 	};

 always_comb_or_latch: