github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-03-29 19:50:26 +00:00
Code Issues Releases Wiki Activity

abc9_ops: move assert

Browse Source
This commit is contained in:
Eddie Hung
2020-04-21 15:44:56 -07:00
parent ed7cb0b095
commit b65610fb62
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/abc9_ops.cc
View File

@@ -263,9 +263,9 @@ void prep_bypass(RTLIL::Design *design)
auto derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
if (!inst_module->get_bool_attribute(ID::abc9_bypass))
continue;
log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
// The idea is to create two techmap designs, one which maps: