github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-10 16:09:25 +00:00
Code Issues Releases Wiki Activity

Workaround issues exposed by gcc-4.8

Browse Source
This commit is contained in:
Eddie Hung
2019-06-21 14:23:39 -07:00
parent bd7ec673dd
commit b75863ca3f
1 changed files with 7 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
frontends/aiger/aigerparse.cc
View File

@@ -117,13 +117,20 @@ struct ConstEvalAig
RTLIL::Cell *cell = sig2driver.at(output);
RTLIL::SigBit sig_a = cell->getPort("\\A");
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
if (!inputs.count(sig_a))
compute_deps(sig_a, inputs);
if (cell->type == "$_AND_") {
RTLIL::SigSpec sig_b = cell->getPort("\\B");
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
if (!inputs.count(sig_b))
compute_deps(sig_b, inputs);
}